The present invention refers to a process to obtain multielement linear bidimensional infrared detectors having improved exactness of geometry and high degree of integration.
More particularly the present invention refers to a process which permits to obtain multielement infrared detectors in which the distance between each element and the next is considerably reduced.
This process is specifically applied to obtain an infrared detector device utilizing a large number of active and passive elements disposed according to a geometry which is fixed and optimizated according to the system in which the device will be utilized.
One of the problems most studied by the technicians who operate in the multielement IR detector field is, as it is well known, to reduce as much as possible the distance between each element and the next. It must be pointed out that the reduction of said distance in a detector, implies the reduction of the surface not utilized for detecting the infrared radiation or in other words the reduction of that amount of radiation which is not detected because is exactly focused between two consecutive elements. In the case of parallel-scanning of the scene, this feature is very much important.
The diameter of a scan measured between points having as intensity equal to half of the maximum obtainable by a f/1 optics, for a typical wave-length of 5 .mu.m, is about 10 .mu.m.
Thus, the distance between the elements in a IR detector should be at least of the same quantity range. In the prior art technologies the separation of the single detector from the others is obtained as follows. Starting from a semiconductor chip having the desired thickness, a groove is engraved or dug as deep as the thickness of the chip to permit the separation of the detectors.
There are many engraving methods like chemical etching, ionic erosion, etc.
Nevertheless they have all one common feature: the engraved walls are not completely perpendicular to the chip surface but are slightly oblique inwardly toward the groove. Optimistically, it can be assumed that the slope rate is about 0.5.
This means that if the chip has a thickness of 20 .mu.m, each wall of the groove will reach inwardly about 10 .mu.m. Then the smallest distance obtainable between the superior surfaces to be utilized of two consecutive elements cannot be less than 20 .mu.m which is twice the desired optimum value.
On the other hand, it must be pointed out that technological reasons do not allow to use chips having a thickness less than 20 .mu.m.
An attempt to overcome this difficulty has been made by utilizing the element by element assembling process.
This solution involves deterioration of alignment and planarity values of the elements and then of the entire surface offered to the radiation.
A further disadvantage of this assembling process is represented by the fact that it involves increased number of technical steps and then an increased cost and assembling time.